1. Field of the Invention
The present invention relates to the design of electronic circuit, and more specifically to a method and apparatus to synchronize an input clock signal to a sampling clock signal and generate a synchronized clock signal.
2. Related Art
Clock signals are generally used to coordinate and control the operation of various components/devices. In general, the edges of a clock signal provide a time reference at which activities such as transitioning to a next state, sampling a signal on a path, etc, can be performed.
There are several situations in which environments operate in multi-clock domains. A multi-clock domain generally contains multiple clock signals, which are generated independently such that the clock signals potentially do not have a phase and/or frequency relationship. For example, a portion of an integrated circuit (IC) may operate based on one clock signal and another portion of the IC may operate based on another clock signal.
There is often a need to synchronize a clock signal in one domain to a clock signal in another domain. In general, clock synchronization (hereafter simply “synchronization”) refers to timing the edges of a clock signal in one domain to the edges of the clock signal in the another domain. In the present application, the clock signal in the one domain is referred to as a input clock signal, the clock signal in the another domain is referred to as a sampling clock signal, and the clock signal generated is referred to as a synchronized clock signal.
Such a synchronization is often used when there is signal/data transfer from one domain to the other. For example, a module operating in one clock domain may need to send data to another module operating in another clock domain, and a common clock reference may be desirable to send data from one module to the other. The common clock reference generally simplifies the reception of the data. A synchronized clock signal provides the desired common clock reference.
At least for reasons such as those noted above, there is a general need to synchronize an input clock signal to a sampling clock signal and generate a synchronized clock signal.